Semiconductor technology continues to update and iterate, and MCU must also keep pace with the times. In order to better meet future trends, some manufacturers choose to start from the core, such as switching from the Arm Cortex-M core to the RISC-V core; some choose to integrate AI, and make the MCU more intelligent by adding an AI accelerator to the MCU; There is one that is mainly introduced next - integrating new types of memory.
As a chip that needs to integrate CPU, SRAM, non-volatile memory and special peripherals, MCU mainly includes eDRAM, SRAM volatile memory, flash memory, and EEPROM non-volatile memory. Among them, integrated flash memory is an important feature of MCU, but as time goes by, flash memory has become one of the bottlenecks restricting MCU from improving performance and reducing power consumption.
On the one hand, it is difficult to expand the process of flash memory below 40nm, while MCU has already begun to move towards 28nm, and these memory cells are not easy to integrate into very complex high-K metal gate technology.
On the other hand, the rewritable times of the flash memory integrated in the vehicle-mounted MCU are too small. With each write and erase cycle, the tunnel oxide in the floating gate NOR unit will degrade and the leakage will increase, thereby accelerating the aging of the flash memory. making it unsuitable for data storage.
In addition, although the emergence of flash memory has changed the difficulty of erasing program data brought about by ROM in the past, it still takes a long time to write to embedded flash memory, partly because it needs to be erased before writing. , which causes the main MCU, which runs two to three orders of magnitude faster than flash memory, to have to wait for memory accesses, all of which have the potential to adversely affect MCU performance.
Based on the factors described above, more and more MCU manufacturers have begun to choose to integrate new types of memory in MCU, such as phase change memory (PCM), magnetic RAM (MRAM) and resistive change memory (RRAM). Of course, different MCU manufacturers There are also different options...
Fast read and write, STMicroelectronics chooses PCM
In terms of new memory, STMicroelectronics has been an early researcher of phase-change memory (PCM) embedded in microcontrollers, especially for automotive applications. The full name of PCM is Phase-change RAM (Phase-change RAM), which can also be called PCRAM. Its principle is to change the temperature of the phase-change material between the low-resistance crystalline (conductive) state and the high-resistance amorphous (non-conductive) state. .
The basic mechanism of PCM was invented by Stanford Robert Ovshinsky in the 1960s. It is made of germanium antimony tellurium (GST) alloy and uses the rapid thermal control change of material flow characteristics between amorphous and crystalline states to read and write at low voltage. , has several significant advantages over flash memory and other embedded memory technologies, such as low latency, write performance/data retention, long life, low power consumption, high density, good radiation resistance, and flexible back-end processes and many other technical features.
Perhaps because of its excellent performance, PCM took the lead on the stage of MCU. According to related reports, among the production technologies after the 28nm generation, the eNVM technology first released by MCU manufacturers is ePCM. In 2018, STMicroelectronics announced that the technical structure and performance standards of the 28nm FD-SOI automotive MCU with built-in ePCM began to provide major customers with ePCM and MCU samples.
According to the news, STMicroelectronics is the first manufacturer capable of integrating this non-volatile memory and 28nm FD-SOI technology, and developing a high-performance low-power automotive MCU. In fact, STMicroelectronics began researching PCM as early as 2000 and cooperated with Intel. In 2005, STMicroelectronics and Intel jointly developed 90nm PCM technology. In 2008, the two companies merged their respective discrete memory businesses and established Numonyx. NV JV, subsequently acquired by Micron (Boise, ID).
The reason why PCM is suitable for vehicle applications is mainly due to the creativity and cost of PCM. For example, in automotive applications, the integration of ePCM storage elements is much cheaper than 28nm embedded flash memory; ePCM improves fast read and write, shortens factory programming time, and reduces manufacturing costs; allows the single-bit programmable Changeability, significantly reducing system write times; improving reliability and endurance advantages comparable to embedded flash, allowing more writes.
At present, STMicroelectronics' MCU equipped with ePCM is mainly used in the automotive field. In 2018, STMicroelectronics stated that the ePCM solution can overcome the demand for larger embedded memories in automobiles, and its maximum operating temperature can reach +165°C, which can ensure its firmware/ The data can be preserved in good condition, and it is anti-radiation, providing more security protection for the data. By August 2021, STMicroelectronics began to deliver its first batch of Stellar SR6 series automotive MCUs to major car manufacturers, and mass production is planned for 2024. Among them, the first MCUs of the Stellar SR6 P and G series are equipped with up to 20MB PCM, which ensures excellent read and write performance, long data retention period, and meets AEC-Q100 grade 0 automotive standards.
Infineon chooses RRAM
Infineon, one of the well-known MCU manufacturers, chose RRAM (ReRAM). On November 25, Infineon announced that it was preparing to introduce TSMC's RAM non-volatile memory (NVM) technology into Infineon with TSMC, the foundry leader. In the next generation of AURIM MCU.
Resistive Random Access Memory, the full name is Resistive Random Access Memory, ReRAM or RRAM for short. As the simplest storage technology, RRAM works by changing the resistance of the dielectric. Applying just the right voltage on the dielectric creates tiny conductive filaments that allow current to flow, and can reversibly switch between high-resistance and low-resistance states.
Since RRAM can combine the reading and writing speed of DRAM with the non-volatility of SSD, it has the advantages of high erasing and writing speed, strong durability, and the ability to store multiple bits of data in a single storage unit. It also has a very important advantage, that is, low power consumption.
The energy required to store a bit of value in RRAM is less than the energy required to store a bit in flash memory technology. Each memory cell in RRAM can be set or reset independently of other cells, but in flash memory, the entire block must first be erased, increasing the workload of data management. Furthermore, compared to flash memory, the design of the RRAM memory block is less complex, the high-voltage generator is not necessary, and the complex structure of transistors with double gates is replaced by transistors and modified vias. Therefore, RRAM memory seems to be an ideal backup memory for low-power microcontrollers.
Infineon's official news shows that RRAM technology has created great potential for performance expansion, power consumption reduction and cost improvement. It has shipped its AURIX TC4x series samples to major customers based on TSMC's 28nm eFlash technology. The first batch of samples based on 28nm RRAM technology will be Available to customers by the end of 2023. In a sense, RRAM manufactured with 28nm process may bring surprises in terms of size, power consumption and speed.
Flexible use of flash memory - Renesas chooses MRAM
Among the various technologies of eNVM, Renesas, a Japanese MCU manufacturer, chose MRAM. The full name of MRAM is Magnetic RAM (magnetic memory). It is a technology based on the tunneling magnetoresistance effect. It has the technical characteristics of non-volatility, unlimited read and write times, fast writing speed, low power consumption, and high integration of logic chips.
At present, the mainstream MRAM technology is STT-MRAM (spin injection MRAM). As a variant of MRAM, the spin of its accessory electrons will affect the polarity of MTJ (magnetic tunnel junction). Compared with other forms of MRAM, STT-MRAM has lower power consumption and the ability to further expand, although STT-MRAM has comparable performance to DRAM and SRAM, such as even if the power is cut off, information will not be lost, and DRAM It can also be randomly accessed; the erasable number exceeds 1015 times, which is equivalent to DRAM and SRAM, and greatly exceeds the 105 times of flash memory, etc., but it seems that it can also be realized in a process below 10nm. IMEC once held at the 2018 IEEE IEDM conference Demonstrated the feasibility of introducing STT-MRAM as the last level (L3) cache memory at the 5nm technology node, so many people think that STT-MRAM will change "memory (hard disk and NAND flash memory) to non-volatile, higher-level Memory (DRAM and SRAM) is volatile" traditional computer architecture, is expected to become a leading storage technology.
Renesas focuses on STT-MRAM and continues to develop new technologies for it. At the IEDM2021 at the end of last year, Renesas announced that it has confirmed that it has reduced power consumption and increased the write operation speed on the 16nm FinFET logic process embedded STT-MRAM test chip.
Renesas said that MRAM requires less energy for write operations than flash memory, making it particularly suitable for applications with frequent data updates, but as demand for MCU data-processing capabilities surges, so does the need to improve the trade-off between performance and power consumption , further reducing power consumption is still a pressing issue. To meet this need, Renesas has developed two technologies for MRAM, a self-terminating write scheme using slope pulses and simultaneous write bit number optimization technology. Finally, measurements performed by Renesas on a 20 Mbit embedded MRAM memory cell array test chip using a 16nm FinFET logic process confirmed that the combination of the above two technologies can reduce the write energy by 72% and reduce the write pulse application time 50% shorter.
However, Renesas also pointed out that the read margin of MRAM is too small, which will reduce the read speed, which will affect the performance of the MCU. Therefore, it is necessary to further increase the speed to shorten the system downtime for over-the-air (OTA) updates required by endpoint devices. This Renesas has developed a fast read technology using a high-precision sensitive amplifier circuit and a fast write technology that optimizes the number of simultaneous write bits and shortens the mode transition time, and has been verified to achieve random read access of 5.9 ns and 5.8 ns on a test chip. MB/s write throughput. Renesas believes that these new technologies have the potential to significantly increase memory access speeds beyond 100 MHz, enabling MCUs with higher performance integrated embedded MRAM.
It is worth mentioning that, unlike Infineon and STMicroelectronics, which are used in automotive electronics, according to official news from Renesas, its MCU integrating STT-MRAM technology is currently mainly used in the field of Internet of Things. As for whether it will turn to automotive electronics in the future field, we will wait and see.
Emerging storage technologies, who will be the future choice
So, among the many emerging storage technologies, who will be the future choice? At present, PCM must be at the forefront. After all, the MCU samples integrating PCM have been shipped, and the mass production time is just around the corner. However, it should be noted that PCM is not a perfect choice, and it also has certain limitations.
First, the cooling process after PCM RESET requires high thermal conductivity, which will lead to higher power consumption, and because its storage principle is to use temperature to realize the resistance change of phase change materials, it is very sensitive to temperature and cannot be used in wide temperature Scenes.
Second, in order to make phase-change materials compatible with CMOS technology, PCM must adopt a multi-layer structure, so the storage density is too low to replace NAND Flash in terms of capacity.
Third, because the typical ratio of germanium, antimony, and tellurium elements of PCM is 2:2:5, the melting point is relatively low, and there may be a problem that the pre-programmed memory may be erased when it is soldered to the printed circuit board, although the system Programming can address this temperature limitation, but it also affects the 10-year retention at high temperatures.
In fact, the well-known Intel 3D XPoint memory technology is a type of PCM. Due to the excessive mask required, the cost increases, and the manufacturing difficulty is also very difficult. Although this technology is used in non-volatile memory The field has achieved a revolutionary breakthrough, but it has not escaped the fate of abjection.
On the other hand, although MRAM has better performance, the critical current density and power consumption still need to be further reduced. At present, the size of MRAM memory cells is still large and does not support stacking. The process is relatively complicated. It is difficult to ensure uniformity in large-scale manufacturing, and the storage capacity and yield rate are slow to climb.
Although mentioned above, IMEC demonstrated the feasibility of introducing STT-MRAM as the last level (L3) cache memory at the 5nm technology node at the 2018 IEEE IEDM conference, but in fact this technology has also proved insufficient to expand operations. to a faster, lower level cache (L1/L2). On the one hand, compared to SRAM, the STT-MRAM writing process is still relatively inefficient and time-consuming, posing an inherent limitation on the switching speed (no faster than 5ns). On the other hand, the speed gain will require increasing the current flowing through the MTJ, thus flowing through the thin dielectric barrier, so each read and write will cause a small damage to the insulation layer, which will also reduce the durability of the device over time. For L1/L2 cache operation with nanosecond switching speed, STT-MRAM is not a good match.
As for RRAM, its disadvantages are also obvious, the biggest disadvantage being severe device-level variability. Device-level variability is directly related to the reliability of the chip, but because the transition of the RRAM device state needs to control the drift of oxygen ions driven by an electric field and the diffusion of oxygen ions driven by heat by applying a voltage to the electrodes at both ends, so that The three-dimensional shape of the conductive filament is difficult to control, coupled with the influence of noise, it is easy to cause device-level variability.
In addition, although the RRAM array has two mechanisms, the total chip area of the RRAM with the 1T1R structure depends on the area occupied by the transistor, so the storage density is low; while the RRAM with the Crossbar structure has a high storage density, but there is a voltage on the interconnection line Dropping and sneaking current paths, causing problems such as decreased read and write performance, increased energy consumption, and write interference.
All in all, each storage technology has its own advantages and disadvantages, and there is no perfect existence. How do MCU manufacturers make trade-offs? How to develop new technologies for weak areas as much as possible? And how to develop new equipment and new materials needed for emerging technologies? These are issues that cannot be ignored and need to be considered, but one thing can be confirmed, that is, even MCU manufacturers must pay close attention to the development and trend of emerging storage technologies, otherwise they will be left behind by competitors.
